VHDL-AMS compile error Need Solution

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Hello,

I'm getting the following error as I try to do so.

I tried to create a testbench includes a transducer written in VHDL-AMS and some standard components By analogLib. I get the error in this point; I try Netlist and run a transient solution.

 
file: /usr/local/cds-een/cadence/ius/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams
ncvlog: *E,DLPAKW: Attempt to write connect connectLib.ConnRules_18V_full_fast:connect (VST) into a read-only library.
    connect connectLib.ConnRules_18V_full_fast:connect
 
Please somebody give me a correct solution.
 
Thanks.

 

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Answered By 0 points N/A #156323

VHDL-AMS compile error Need Solution

qa-featured

 

This error particularly indicates that the installation of  IUS or INCISIVE is not well-configured. Therefore, you are required to add the path given below to cds.lib.
 

ASSIGN AllLibs TmpRootDir path

path mention above is the path to an editable directory , which is occasionally under your running directory.  This will enable the acquisition of read-only stuff to get into the directory.

If you to wish make it precisely,   you may use

ASSIGN connectLib TMP path

Thus, this will be executed  for connectLib solely.

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