JTAG Test Failed: Serial Bus Error

Asked By 820 points N/A Posted on -


Joint Test Action Group JTAG Test Access Port and Boundary-Scan Architecture.

It is a serial bus with four signals:

  • TCK(Test Clock)
  • TMS(Test Mode Select)
  • TDI(Test Data Input)
  • TDO(Test Data Output)

The bus is used as a test bus for the Boundary-Scan of ICs, as in Design-For-Testability.

For my official project, whenever I test the circuit with it, I got the following error.

Jtag error


JTAG test failed

Failed – TDO changes, but TDI pattern does not match.

Try the following hints to fix the problem:

  • Try to use lower JTAG clock frequency.
  • Do no0t use extra adapters, but use JTAGjet probe which matches your target connector.
  • Make sure, that extra on-board buffer on JTAG lines are disabled (if possible)>
  • Verify if pull-uppull-down resistors are in recommended range.
  • Consult documentation (Help button) for more JTAG-problem solving hints.

I inspect every possible area where there might be a chance for error, but every thing is fine enough according to my technical knowledge.

I am therefore presenting this error to the experts here to guide me how to check and resolve this problem.


Answered By 0 points N/A #119497

JTAG Test Failed: Serial Bus Error


Hey Rowan,

The following pre-conditions ensure that the hardware setup is functioning properly.

Step 1:


Check the JTAG cable and ensure that there is continuity for individual wires (The desired resistance is in the range of 0.5 Ohm).

Step 2:

Check the UAD (Universal Access Device) and ensure that it is working properly. For checking this there will be a status LED on the device and the normal functioning of the device should be as per the user manual. The software should have a provision to check the UAD status. Please explore this also.

Step 3:

Ensure that the USB cable from the PC to the UAD is proper.  Also, check the power adapter to the UAD (Check the voltage and current output of the adapter using a Multimeter).  

Hope this helps.


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