Compilation error on FPGA VI
I was using a 9861 NI-XNET module in a CompactDAQ form factor configured for FPGA mode with a DMA FIFO. However, when the FPGA VI was compiled, an error message (see screenshot below) popped up during the generation of intermediate files.
Any advice on how to get rid of the problem?
Code Generation Error
Items with Errors
The current target does not have sufficient DMA control line sets available
Resource: ’FIFO’(read Interface)
Too many sets of DMA controls lines have been requested or some requests are conflicting. The current target has 4 sets of DMA control lines. Review the list of requesters and remove one or more requesters to free up resources.