Flow of Code and Data

Here is the flow of data from Random Access Memory that are being accessed by the CPU or the processor. The instruction of data may consist of address of the location of the Random Access Memory. This is where the data is to be read and being brought to the CPU if it needs further processing. This data is sent then to the Random Access Memory controller where it manages the request and send it to the suitable address lines. The transistors along the lines unlock the cells so that the value of the capacitor could be read. The data that is read is then conveyed along the lines to the other processor’s data buffer known as level-1 or level-2 cache.  Hope this will help you. Thank you.