I have been developing a MIMO transceiver for real time by the use of FLEXRIO hardware and Lab VIEW FPGA with CLIP.
When it is combining a new FPGA via, the error message below displays on the PC screen.
If any of you guys can give me some help, I would be very grateful because I have done I lot of work on this and I will be very sad if this become a waste of time.
Thank you for reading this because I know you will give me a solution.
Primary Software: Lab VIEW Modules > Lab VIEW FPGA Module
Primary Software Version: 2011
Primary Software Fixed Version: N/A
Hardware: Modular Instruments > FlexRIO > PXIe - 7965R
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